The present invention relates to a semiconductor device and a process for manufacturing the same.
In recent years, the dimension of each component of semiconductor elements, in particular the dimension of the gate length tends to decrease as the semiconductor devices tend to be smaller and faster in its speed. A process for manufacturing such a prior art semiconductor device will be described with reference to FIG. 3. FIGS. 3(A) through 3(D) are sectional views schematically explaining a process for manufacturing the prior art semiconductor device.
Firstly, as shown in FIG. 3(A), a silicon substrate 1 is formed thereon with element isolating areas 2 by using, for example, a trench isolating and forming process and is then formed with a gate oxide layer 8. Then, a polycrystal silicon layer 15 and the like designed to become a gate electrode 9 is formed thereon as shown in FIG. 3(B), Subsequently, a resist pattern 6 for forming a gate electrode 9 is formed. The polysilicon layer 15 is then etched using the resist pattern 6 as a mask as shown in FIG. 3(C). Thereafter, a lightly doped drain (LDD) area 10 is formed by implanting ions of arsenic or phosphorus, and boron or boron fluoride into N and P channel areas, respectively, at a dose rate of 5E12 cmxe2x88x922 to 2-5E14 cmxe2x88x922 by an ion implanting process. The LDD configuration is effective for forming a short channel transistor.
Subsequently, a sidewall 7 having a thickness of 30 nm to 100 nm is formed of, for example, a silicon oxide layer externally of the gate electrode 9. Thereafter, source/drain areas 3 designed to become defused layer areas are formed by implanting ions of arsenic or phosphorus, or boron or boron fluoride into N or P channel areas, respectively, at a dose rate of 1E15 cmxe2x88x922 to 2-1E16 cmxe2x88x922 by the ion implanting process.
Then, an interlayer insulator layer 11 is formed as shown in FIG. 3(D) and is then a resist pattern for forming a contact 12 is formed. Thereafter, the interlayer insulator layer 11 is etched using the resist pattern as a mask. This etching is conducted under such a condition that a selection ratio between the silicon oxide layer 5 and the interlayer insulator layer 11 can be adjusted. Thereafter, the inside of the contacts is filled with, for example, tungsten and then wiring 13 is formed. A semiconductor device is thus manufactured.
However, the gate length can not be made shorter than the limitation of the lithography in the above-mentioned prior art process for manufacturing the semiconductor device. Also the source/drain areas 3 should be formed deeper than the gate electrode 9. Accordingly, there is a problem in that a short channel effect in which the breakdown voltage between the source and drain areas 3 is lowered so that occurrence of a punch through is liable to occur cannot be suppressed.
Furthermore, the element isolation areas 2 would be etched upon etching of the contact (hole) 12 if the contact (hole) 12 is formed opening above the element isolation area 2. Accordingly, the element isolation area 2 would be dug. A problem will occur in that a leakage between the contact 12 and the silicon substrate 1 takes place.
Generally, the present invention aims at overcoming the above-mentioned problems. It is therefore a main object of the present invention to provide a semiconductor device and a process for manufacturing same, which is capable of suppressing the short channel effect and preventing the leakage of current between the contact and the silicon substrate. Other objects will become apparent in the entire disclosure.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: a trench which splits a source/drain layer formed on a semiconductor substrate and has such a depth that it reaches the semiconductor substrate; and a columnar gate electrode which is disposed within the trench at a position which is spaced from a sidewall of the trench.
According to a second aspect, there is provided a semiconductor device comprising: a trench which splits a source/drain layer formed on a semiconductor substrate having a lightly doped drain (LDD) layer and the source/drain layer successively formed thereon in this order and has such a depth that it reaches the lightly doped drain layer; a doped area beneath the trench, which splits the lightly doped drain layer and reaches the semiconductor substrate; and a columnar gate electrode which is disposed within the trench at a position spaced from a sidewall of the trench.
A third aspect of the present invention resides in a semiconductor device characterized in that a semiconductor substrate is successively formed with a source/drain layer, a silicon oxide layer and a silicon nitride layer in this order at an area lying between element isolating areas; and in that the device comprises a trench having such a depth that it extends through the source/drain layer, the silicon oxide layer and the silicon nitride layer to reach the semiconductor substrate; a columnar gate electrode which is formed with the trench at a position spaced from a sidewall of the trench and abuts to the semiconductor substrate through a gate oxide layer; and a lightly doped drain layer which is formed at an area which is not covered with the gate electrode, within an area where the semiconductor substrate is in contact with the trench.
A fourth aspect of the present invention resides in a semiconductor device characterized in that a lightly doped drain layer, a source/drain layer, a silicon oxide layer and a silicon nitride layer are successively formed in order on a semiconductor substrate at an area between element isolating areas; and in that the device comprises a trench having such a depth that it extends through the source/drain layer, the silicon oxide layer and the silicon nitride layer to reach the semiconductor substrate; a columnar gate electrode which is formed with the trench at a position spaced from a sidewall of the trench and abuts to the semiconductor substrate through a gate oxide layer; and a lightly doped drain layer which is formed at an area bebeath the gate electrode, within an area where the semiconductor substrate is in contact with the trench.
A fifth aspect of the present invention resides in a process for manufacturing a semiconductor device characterized in that the process comprises the steps of: (a) forming element isolating areas on a semiconductor substrate; (b) forming a source/drain layer of a transistor by an ion implanting process; (c) successively laminating a silicon oxide layer and a silicon nitride layer in this order; (d) forming a trench having such a depth that it reaches the semiconductor substrate by etching the silicon nitride layer, the silicon oxide layer and the source/drain layer by using a resist pattern as a mask; (e) forming a sidewall on an inner wall of the trench; (f) filling a space surrounded by the sidewall of the trench with a first electrically conductive material designed to become a gate electrode; (g) removing the sidewall; (h) forming a lightly doped drain layer by implanting ions via an area in which the sidewall has been removed; (i) forming an interlayer insulator layer over an entire of the semiconductor substrate; (j) forming a contact hole by etching through the interlayer insulator layer, the silicon nitride layer and the silicon oxide layer; and (k) forming a predetermined wiring after embedding the inside of the contact hole with a second electrically conductive material.
A sixth aspect of the present invention resides in a process for manufacturing a semiconductor device characterized in that the process comprises steps of: (a) forming element isolating areas on a semiconductor substrate; (b) forming a source/drain layer of a transistor by an ion implanting process; (c) successively laminating a silicon oxide layer and a silicon nitride layer in this order; (d) forming a trench having such a depth that it reaches the semiconductor substrate by etching the silicon nitride layer, the silicon oxide layer and the source/drain layer by using a resist pattern as a mask; (e) forming a sidewall on an inner wall of the trench; (f) forming a doped area which splits the lightly doped drain layer below the trench by implanting a dopant by using the sidewall as a mask; (g) removing the sidewall; (h) forming a lightly doped drain layer by implanting ions via an area in which the sidewall has been removed; (i) forming an inter layer insulator layer over an entire of the semiconductor substrate; (j) forming a contact hole by etching through the interlayer insulator layer, the silicon nitride layer and the silicon oxide layer; and (k) forming a predetermined wiring after embedding the inside of the contact hole with a second electrically conductive material.